Google and Synaptics Bring Open-Source Coral AI Silicon to Wearables and Edge Hardware

TL;DR: Google and Synaptics have unveiled a new family of low-power processors that pair open-source Coral NPU silicon with custom memory architectures to run machine learning models directly on smart glasses, industrial cameras, and remote sensors.

The push to decouple machine intelligence from central data centres

For the past several years, the bulk of artificial intelligence investment has flowed into massive hyperscale data centres packed with power-hungry accelerators. While these facilities excel at training foundational models and serving large cloud queries, they present clear operational limits for mobile hardware, field equipment, and industrial robotics. Relying on continuous cloud connectivity introduces latency, strains wireless bandwidth, and drains battery life rapidly. When a wearable device or a factory sensor must transmit continuous audio or video streams over cellular or Wi-Fi links simply to parse what it observes, the architecture quickly breaks down.

To bridge this gap, Google Research and semiconductor designer Synaptics have joined forces to deliver a new class of edge silicon designed specifically for constrained environments. Through the introduction of the Astra SR200 processor family, Synaptics is incorporating Google's open-source Coral neural processing unit (NPU) architecture into commercial silicon. The objective is clear: make on-device inferencing computationally viable for everyday smart glasses, acoustic monitors, and ruggedized edge endpoints without relying on an external server or an oversized battery pack.

By targeting workloads that operate under strict thermal and electrical envelopes, the joint initiative reflects a broader shift across the technology landscape. Compute is decentralizing, migrating out of the server rack and directly onto the physical endpoints where real-world operational data originates.

An open-source NPU architecture built on RISC-V

The technological core of this partnership rests on an unusual silicon strategy from Google. Historically, hardware accelerators developed by major technology companies remain tightly guarded proprietary assets, intended either for internal data centre operations or restricted to proprietary consumer lineups. However, Google Research took a fundamentally different approach when it opened the Coral NPU architecture under the permissive Apache 2.0 license.

Based on the open RISC-V instruction set architecture, the Coral design allows semiconductor companies to adopt, modify, and fabricate hardware accelerators without paying licensing fees or ongoing royalties to Google. The goal of this initiative is to standardize edge development environments. In the fragmented world of embedded microcontrollers, software engineers routinely face incompatible proprietary compilers and toolchains for each chipmaker. By making Coral open and backing it with modern compiler toolchains, Google is attempting to lower the barrier for porting neural networks across multiple silicon platforms.

Synaptics serves as Google's initial commercial silicon partner under this framework. To bridge the gap between machine learning frameworks and the physical circuits, Synaptics relies on its open-source Torq compiler, which is built on the industry-standard MLIR and IREE projects. This software layer translates models compiled in standard environments such as PyTorch, JAX, and LiteRT directly into executable machine code for the integrated Coral NPU, minimizing the manual hardware optimization usually required in embedded systems.

Under the hood of the Astra SR200 family

The Astra SR200 lineup is divided into three distinct silicon tiers, calibrated to balance compute throughput against strict power constraints. Rather than deploying high-wattage application processors, Synaptics built the SR200 series around power-efficient Arm Cortex-M cores coupled directly with the Coral accelerator.

At the entry level, the Astra SR210 is tuned for persistent, always-listening acoustic analysis and low-bandwidth sensor monitoring, delivering 200 billion operations per second (GOPS) of artificial intelligence throughput. Moving up the tier, the SR230 increases performance to 300 GOPS while integrating hardware pathways for camera interfaces and basic visual display output. The flagship model, the SR250, reaches 400 GOPS, providing sufficient computational headroom for multimodal models that evaluate visual imagery and voice inputs simultaneously.

Raw processing throughput, however, is only one piece of the edge computing challenge. Running modern language or vision models locally requires sufficient memory bandwidth and storage. Standard dynamic RAM (DRAM) is among the most power-hungry components in small electronics. To counteract this, Synaptics integrated up to 8MB of internal static RAM (SRAM) and introduced specialized high-density DRAM packaging options reaching up to 256MB on its upcoming development hardware. Synaptics claims this custom memory architecture draws roughly one-third of the operational power demanded by conventional system DRAM during similar workloads.

This architectural arrangement enables embedded devices to retain intermediate neural network weights and process camera frames entirely within a low-power envelope, eliminating the requirement for separate, energy-intensive memory chips.

Running compact vision and language models on the edge

The hardware is arriving alongside a major industry trend toward parameter-efficient, compact machine learning architectures. While multibillion-parameter models require rack-mounted server hardware, a new class of sub-billion-parameter models has emerged to handle focused tasks on local endpoints.

Among the workloads targeted for the Astra SR200 platform is Google's Gemma 3 270M model, a highly compressed text and multimodal network. According to performance figures shared by Synaptics, the architecture can execute Gemma 3 270M at speeds ranging between 12 and 16 tokens per second, depending on the chosen quantization and compression parameters. For interactive applications, such as a hands-free headset offering field guidance or voice-driven operational prompts, this speed is more than adequate for real-time interaction.

Beyond language processing, the platform is engineered to support computer vision backbones such as Ultralytics YOLO along with Liquid AI's LFM2.5 architectures. These models allow connected hardware to conduct real-time object classification, anomaly detection, and facial verification locally. Hardware partners exploring the ecosystem include augmented reality specialist Jorjin Technologies, home audio brand Sonos, and industrial security system provider Verisure.

Developer hardware availability and market dynamics

To seed the engineering community, Synaptics and Google have started distributing physical development boards. Engineers can currently acquire the Coralboard SL through component distributor DigiKey for roughly $99.79. This initial hardware platform runs on Synaptics' Astra SL2619 processor, providing one tera-operation per second (TOPS) of acceleration paired with 2GB of DDR4 memory for broad prototyping work.

A subsequent board, the Coralboard SR, will feature the ultra-low-power SR250 processor and integrated low-power memory architecture once the silicon moves beyond its current initial sampling phase. Synaptics has not yet published single-unit or high-volume pricing for the standalone SR200 microcontrollers.

This product launch arrives at an eventful moment for Synaptics, which is currently working through a planned $5.7 billion acquisition by onsemi, scheduled to conclude by the middle of 2027. It also places the company squarely against established embedded semiconductor players. STMicroelectronics already produces its STM32N6 microcontroller with up to 600 GOPS of proprietary neural acceleration, while Renesas markets its RA8P1 silicon platform with dedicated AI capabilities.

As reported by VentureBeat during an initial technical briefing, Google considers the Coral initiative less of an individual silicon venture and more of a foundational ecosystem play. By standardizing open-source NPU architectures, Google hopes to foster an environment where developers can deploy modern machine learning applications across diverse consumer and industrial form factors without rebuilding their software stack from scratch.

Why it matters

For enterprise operations, field service organizations, and telecommunications providers, the arrival of efficient, open-source edge silicon marks an important shift. Remote technicians working in subterranean utility vaults, offshore wind installations, or heavily shielded data centre halls frequently encounter complete connectivity dead zones. When wearable displays or diagnostic cameras depend entirely on cloud APIs, tools become paperweights the moment cellular reception drops.

Low-power processors that run multimodal models locally ensure that technicians can receive visual component recognition, equipment telemetry analysis, and hands-free spoken diagnostic guidance completely offline. Furthermore, keeping audio and visual data on the physical device resolves thorny enterprise security and privacy issues. Sensitive video feeds from industrial control rooms, private telecom exchanges, and secure manufacturing floors no longer need to traverse public internet networks.

For data centre operators, the local execution of ambient tasks helps stem the unsustainable growth of raw sensor data traffic flooding inbound network interfaces. By filtering, recognizing, and acting upon data directly at the physical perimeter, open-source edge hardware like the Coral-powered Astra series allows centralized cloud infrastructure to focus strictly on complex orchestration rather than continuous low-level monitoring.